1. Field of the Invention
The present invention relates to integrated circuit devices and more specifically to field effect transistors (FET) for use in integrated circuits.
2. Description of the Prior Art
Memories are devices that respond to operational orders, usually from a central processing unit. Memories may store large quantities of information in a digital format. In a memory system or unit, addresses are used to access the contents of the memory unit. A binary digit, also called a bit, is the basic information element stored in a memory unit. The smallest subdivision of a memory unit into which a bit of information can be stored is called a memory cell. A memory on a chip is physically arranged as a two-dimensional array of cells, wherein rows of cells are connected by row lines, also called word lines. A column of cells are connected by a column line, also called a bit line. These memory cells may be constructed by various configurations of transistors and/or capacitors.
A semiconductor memory is a memory that is implemented in a semiconductor material such as silicon. Metal-oxide semiconductor (MOS) memories are common in the industry. A number of different types of MOS memories exist, such as a dynamic random access memory (DRAM) which is a metal oxide semiconductor memory that stores a bit of information as a charge on a capacitor, and a static random access memory (SRAM) which includes a bistable flipflop circuit requiring only a DC voltage applied to it to retain its memory. Normally, an SRAM contains four transistors plus either two transistors or two polysilicon load resistors as pull-up devices.
SRAMs have a disadvantage over a memory such as a DRAM. The components in an SRAM typically require the SRAM to have a larger basic cell than a DRAM. In SRAM memory cells, the data transfer gate transistor to pull-down transistor ON resistance ratio is typically required to be about 2.6.times. or greater to provide stability to the memory cell. Currently, the width of the pull-down transistor is required to be larger than the width of the transfer gate transistor to achieve the ratio requirement. This requirement places limitations on how small the memory cell may be made. Therefore, it would be desirable to have a transistor structure that would allow for a reduction in the area that a memory cell requires.